The present invention relates to semiconductor integrated test structures, and more specifically, to in-line test structures for detection of missing conductive layers of a multilayer gate stack in a semiconductor structure.
Semiconductor structures are employing high-k metal gate stacks because they provide better performance at lower power and may avoid leakage resulting from scaling. Hafnium-containing dielectrics are used as gate dielectrics and the gate dielectric is covered by a conductive layer such as titanium nitride (TiN) to protect it during high temperature deposition process of silicon (Si). The conductive layer is then covered by other semiconductor materials, such as an amorphous silicon layer, and may be capped by a silicide cap layer. The gate stack is surrounded by a spacer material. Thus, the conductive layer is typically sealed by the spacer material of the structure. Aggressive cleaning processes are used after the spacer formation process.
One drawback associated with the fabrication process is that if the seal is violated and a path exists to the conductive layer, the conductive layer may be removed during the process. If this occurs, the semiconductor device may not work properly. Detection of a gap in the conductive layer may be challenging using conventional optical or laser-based, voltage contrast (VC), or probeable inspection techniques, because the conductive layer may be covered by other semiconductor material layers.